The process of designing and producing integrated circuit devices is intensive in both time and human capital, requiring the efforts of highly talented and educated individuals. Upon the design of a new integrated circuit, the first die produced must be tested to verify that it is performing in accordance with the design requirements.
The conventional package design for integrated circuit dies has been a plastic package, comprising a metal lead frame and a polymeric insulating material. As the process of encapsulating a die in molded plastic packages can be automated easily, plastic packages are relatively inexpensive compared to ceramic or hybrid hermetic packages. Plastic encapsulation of dies has thus become a mainstay of the electronics industry.
With a few modifications, the basic assembly process for encapsulation packaging of dies can be used to construct a variety of package types. For example, FIG. 1 illustrates a pin-in-hole package: a dual-in-line package (DIP). FIGS. 2-3 illustrate two surface mount packages: a plastic leaded chip carrier (PLCC) and a quad flatpack (QFP), respectively. Each of these plastic packages is constructed from basic assembly techniques known in the art.
Most currently manufactured integrated circuits are packaged or encapsulated in epoxy using the techniques described above. The integrated circuit packaging industry now resides primarily outside of the United States. Because relatively little domestic investment has been made for development of required tooling and equipment for this process, most necessary equipment is also manufactured outside the United States. Therefore, when a domestic company requires packaging of an integrated circuit die, it typically must pay the price for the offshore service and wait the required time for delivery. Added costs and potentially costly marketing delays are consequently created for chip design companies eager to evaluate newly manufactured prototype devices.
Although package construction from ceramic material is an alternative for packaging an integrated circuit die, ceramic packaging is relatively expensive and consequently is used primarily for high performance applications, such as weaponry. If the die design and intended application permits characterization of an alternative packaging method is provided for rapid evaluation of prototype chip designs. In addition to the cost of the alternative packaging, an alternative such as a ceramic package may be a poor substitute for simulating the performance of the die as encapsulated in the manner intended for full-scale production of the device. This is because, depending upon the die's design, the function of the integrated circuit die may be affected by the presence of different encapsulating materials on its surface, and the dimensions of the package conductor paths (leads). If die performance characteristics are sensitive to the encapsulation package, reevaluation and revalidation of the die design may become necessary in the final, production die-package configuration.
Another disadvantage of the use of ceramic packages for prototype units is that the package geometry may necessitate a modification of test sockets and printed circuit boards to receive the prototype ceramic packages for testing and validation of the new die design.
It is thus desirable to be able to test various dies where the dies are encapsulated in the same encapsulant and in a package geometry which allows the various dies to be tested by the same printed circuit boards. A need thus exists for rapid and efficient methods for being able to change dies within a given integrated circuit package and encapsulated by a given encapsulant so that the different dies may be evaluated.